A Deep inside my HTC Desire HD - Main Memory and Cache Memory Structure

Processor (CPU): Qualcomm Snapdragon 2 (MSM8255)

CPU Clock: 1000 MHz

Graphics Processing Unit (GPU): Adreno 205 (accelerating WebGL HTML 5 Video and Flash 10 web content, Stunning 3D  graphics performance for gaming)

CPU Structure: Reduce Instruction Set Computing (RISC)

Instruction Sets: ARM v7 (Processor has von-neumann architecture with single 32 bit data bus carrying both instruction and data.
Load, store, and swap instructions can access data from memory. Data can be 8-bit, 16-bit, and 32-bit.)

Main Memory (RAM): 768 MB (Data can be 8-bit, 16-bit, and 32-bit)

ROM (Type: Flash EEPROM type): 2 GB

Cache Memory:
L1 cache have 32 KB data cache / 32KB instruction cache
L2 cache have 256 KB
Cache Organization Type: 4 way set associative cache organization

Pipelining: 3 stage

• fetch
• decode
• execute

i.e. ARMv7 use 3 stage pipeline to increase the flow of instruction to the processor. This allow multiple simultaneous operation to take place and continuous operation of the processing and memory systems.


resources:
arm.com,
infocenter.arm.com, ...
qualcomm.com, ...
htc.com,
pdadb.com, ...
wikipedia.com, ... ...
ucr.edu